1. Field of the Invention
The present general inventive concept is related to test pattern generation in circuit testing. More specifically, the general inventive concept generates test patterns for residue networks that include overlapping logic cones, varying fan-in, and reconvergent fan-out of its constituent residue circuits.
2. Description of the Related Art
A residue network, as used herein, is a network of one or more logic trees of interconnected residue circuits, alternatively referred to herein as “gates,” each of which computes a residue function, generally the modulo-m sum of its inputs. Such residue networks are used in a wide range of applications, including parity and error correction circuits, and the spreader and compression networks of standard scan configurations of test circuits embedded in primary functional circuitry. A schematic block diagram of such a test circuit 100 is illustrated in FIG. 1. Typically, the test circuit 100 utilizes modulo-2 residue circuits, which may be implemented by binary exclusive-OR (XOR) gates. The scan chains 110-112 are typically constructed as serially connected state retention components, such as flip-flops, that provide test data to the primary functional circuitry and convey response data out of the test circuit 100. An XOR tree configuration is provided at the inputs of the scan chains 110-112 in what is often referred to as a “spreader” network 120, and another XOR tree configuration is provided at the output side of the scan chains 110-112 in what is generally referred to as a “compression” network 130.
As illustrated in FIG. 1, the number of scan chains in the conventional test circuit is NC, the number of scan data input terminals NI, and the number of scan data output terminals NO, where NI<NC and NO<NC. Typically, NI=NO for convenience in assigning and conserving input/output (I/O) terminals, which may be shared by using bidirectional I/O circuits. Thus, the spreader network 120 consists of NC XOR trees, each driven by some subset of the NI scan data inputs, and the compression network 130 consists of NO XOR trees, each driven by some subset of the NC scan chain outputs. The spreader network 120 and the compression network 130 thus minimize the amount of test data that must be scanned into and out of the scan chains 110-112, so that smaller numbers of scan data input terminals and scan data output terminals are needed. Test data are input onto the NI input terminals, where they are decompressed in the spreader network 120, are shifted as decompressed test data through the scan chains 110-112, where they are introduced to the circuit to be tested. Response data are obtained and are subsequently compressed in the compression network 130, and the compressed data are output on the NO output terminals. Additional circuitry may be used, such as a multiple-input signature register (MISR; not illustrated), to further compress the data at the output of the scan chains 110-112.
Traditional scan chain testing, however, does not exercise the residue circuitry in the spreader/compression networks to the extent that these networks are known to be fault-free. Without the knowledge of whether the compression/decompression logic contains faults, detected faults in subsequent logic testing cannot easily be diagnosed. Moreover, the testing of the circuitry is preferably to be carried out using a minimal number of test patterns so that circuit testing consumes less time.
One technique that considers the minimal number of tests as preferential is to note any faults within the compression and decompression logic uncovered during scan chain testing so that those faults are not targeted by the logic tests. With this solution, the expectation is that the scan processes performed during the application of the logic tests would serendipitously detect any failures within the compression and decompression logic. However, since this technique does not identify faults in the compression and decompression networks separately from those of the logic under test, the diagnosis of logic test failures is made even more arduous than it already is.
Another conventional technique is to repeat the scan chain test using random vectors. This approach has a disadvantage that a fixed number of random patterns cannot guarantee detection of all the faults within the compression and decompression logic. Although this can be overcome by monitoring the fault coverage through simulation of the tests and stopping when all the faults have been detected, this random-pattern approach results in an exorbitant number of tests.
Test pattern generation techniques applicable to general residue networks exist, and may be applied to generate test pattern sets for certain restricted residue architectures. However, these general techniques are limited as to their applicability to practical circuits, such as when the residue network contains varying fan-in (the set of input paths to a particular gate) among its constituent components, and/or when the residue network contains reconvergent fan-out (the set of output paths from a gate). Thus, the need has been felt for methods and apparatuses that generate minimal sets of test patterns to test residue networks containing overlapping logic, varying fan-in and reconvergent fan-out, such as in the compression/decompression networks in a test circuit.